ENGR-435 Digital Design II (spring 2021)

HW Announcements & Notes (most recent first)

• HW7 definition. __________due__5/24/21
• HW6 definition. __________due__5/19/21
• HW5 definition. __________due__5/12/21
• Exam 1 planning (pdf)
• HW4 definition. __________due__4/28/21
• HW3 definition. __________due__4/19/21
• HW2 definition. __________due__4/7/21
• HW1 definition. __________due__4/5/21
• Introduction lecture (pdf)

• HW4 solution (pdf)
• HW2 solution (pdf)
• HW1 solution (pdf)

• Syllabus

• Lab 6 definition
  • Notes re debugging & making it work (pdf)
  • DAC driver block diagram (pdf)
  • DAC driver timing diagram (pdf)
  • DAC driver state diagram (pdf)
  • DAC driver IP (vhd)
  • Waveforms workspace file for FIR debugging (.dwf3work)
• Lab 5 definition
  • Notes on ADC data handling (pdf)
  • ADC driver block diagram (pdf)
  • ADC driver timing diagram (pdf)
  • ADC driver state diagram (pdf)
  • ADC-DAC PMOD board schematic (pdf)
  • ADC-DAC PMOD board pinout (pdf)
  • ADC interface circuit IP (vhd)
  • ROM IP with example coefficients (vhd)
  • ROM with 32tap 400hz lowpass coeff 20Khz sample rate (.vhd))
  • ROM with 32taps, 8 sets of data, 50Khz sample rate (.vhd))
  • Example VHDL for range selection (vhd)
• Lab 4 definition
  • Lab 4 block diagram (pdf)
  • ROM IP for sine wave generation (vhd)
• Lab 3 definition
  • PMOD DAC pin numbers
  • DAC timing diagram
  • PMOD1 pinout diagram
• Lab 2 definition
  • VHDL for 4-bits binary to 7-segment display
• Lab 1 definition
  • VHDL for the "machine" module
  • State diagram for the "machine" module (pdf)

• Binary to 7-segment ROM decoder data (pdf)
  
• 8x16 LED display operation description (pdf)
• 8x16 LED array driver block diagram (pdf)
• 8x16 LED display connection details (pdf)
• 8x16 LED display schematic (pdf)
• VHDL listing of the 8x16 LED array driver (vhd)
• VHDL listing of the lab 8 "magic" component (vhd)
• How to test the 8x16 display (pdf)

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