CMSIS-Core (Cortex-M)  Version 5.1.1
CMSIS-Core support for Cortex-M processor-based devices
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System Partition Header File partition_<device>.h

The System Partition Header File partition_<device>.h contains the initial setup of the TrustZone hardware in an Armv8-M system. The function TZ_SAU_Setup is call from SystemInit and uses the settings in this file to initialize the Secure Attribute Unit (SAU) and define non-secure interrupts (register NVIC_INIT_ITNS). The following initializations are performed:

SAU CTRL register settings

#define Value Range Default Description
SAU_INIT_CTRL 0 .. 1 0 Initialize SAU CTRL register or not
  • 0: do not initialize SAU CTRL register
  • 1: initialize SAU CTRL register
SAU_INIT_CTRL_ENABLE 0 .. 1 0 enable/disable the SAU
  • 0: disable SAU
  • 1: enable SAU
SAU_INIT_CTRL_ALLNS 0 .. 1 0 value for SAU_CTRL register bit ALLNS
  • 0: all Memory is Secure
  • 1: all Memory is Non-Secure

Configuration of the SAU Address Regions

#define Value Range Default Description
SAU_REGIONS_MAX 0 .. tbd 8 maximum number of SAU regions
SAU_INIT_REGION<number> 0 .. 1 0 initialize SAU region or not
  • 0: do not initialize SAU region
  • 1: initialize SAU region
SAU_INIT_START<number> 0x00000000 .. 0xFFFFFFE0
[in steps of 32]
0x00000000 region start address
SAU_INIT_END<number> 0x00000000 .. 0xFFFFFFE0
[in steps of 32]
0x00000000 region start address
SAU_INIT_NSC<number> 0 .. 1 0 SAU region attribute
  • 0: Non-Secure
  • 1: Secure, Non-Secure callable

The range of <number> is from 0 .. SAU_REGIONS_MAX. A set of these macros must exist for each <number>.

The following example shows a set of SAU region macros.

#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
#define SAU_INIT_REGION0 1
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
#define SAU_INIT_END0 0x001FFFE0 /* end address of SAU region 0 */
#define SAU_INIT_NSC0 1
#define SAU_INIT_REGION1 1
#define SAU_INIT_START1 0x00200000 /* start address of SAU region 1 */
#define SAU_INIT_END1 0x003FFFE0 /* end address of SAU region 1 */
#define SAU_INIT_NSC1 0
#define SAU_INIT_REGION2 1
#define SAU_INIT_START2 0x20200000 /* start address of SAU region 2 */
#define SAU_INIT_END2 0x203FFFE0 /* end address of SAU region 2 */
#define SAU_INIT_NSC2 0
#define SAU_INIT_REGION3 1
#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
#define SAU_INIT_END3 0x40040000 /* end address of SAU region 3 */
#define SAU_INIT_NSC3 0
#define SAU_INIT_REGION4 0
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
#define SAU_INIT_NSC4 0
#define SAU_INIT_REGION5 0
#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */
#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */
#define SAU_INIT_NSC5 0
#define SAU_INIT_REGION6 0
#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
#define SAU_INIT_NSC6 0
#define SAU_INIT_REGION7 0
#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
#define SAU_INIT_NSC7 0

Configuration of Sleep and Exception behaviour

#define Value Range Default Description
CSR_INIT_DEEPSLEEPS 0 .. 1 0 value for SCB_CSR register bit DEEPSLEEPS
  • 0: Deep Sleep can be enabled by Secure and Non-Secure state
  • 1: Deep Sleep can be enabled by Secure state only
AIRCR_INIT_SYSRESETREQS 0 .. 1 0 value for SCB_AIRCR register bit SYSRESETREQS
  • 0: System reset request accessible from Secure and Non-Secure state
  • 1: System reset request accessible from Secure state only
AIRCR_INIT_PRIS 0 .. 1 0 value for SCB_AIRCR register bit PRIS
  • 0: Priority of Non-Secure exceptions is Not altered
  • 1: Priority of Non-Secure exceptions is Lowered to 0x80-0xFF
AIRCR_INIT_BFHFNMINS 0 .. 1 0 value for SCB_AIRCR register bit BFHFNMINS
  • 0: BusFault, HardFault, and NMI target are Secure state
  • 1: BusFault, HardFault, and NMI target are Non-Secure state

Configuration of Interrupt Target settings

Each interrupt has a configuration bit that defines the execution in Secure or Non-secure state. The Non-Secure interrupts have a separate vector table. Refer to Programmers Model with TrustZone for more information.

#define Value Range Default Description
NVIC_INIT_ITNS<number> 0x00000000 .. 0xFFFFFFFF
[each bit represents an interrupt]
0x00000000 Interrupt vector target
  • 0: Secure state
  • 1: Non-Secure state

The range of <number> is 0 .. (<number of external interrupts> + 31) / 32.

The following example shows the configuration for a maximum of 64 external interrupts.

#define NVIC_INIT_ITNS0 0x0000122B
#define NVIC_INIT_ITNS1 0x0000003A