CMSIS-Core (Cortex-M)
Version 5.1.1
CMSIS-Core support for Cortex-M processor-based devices
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The Device Header File <device.h> contains the following sections that are device specific:
Reference describes the standard features and functions of the Device Header File <device.h> in detail.
Device Header File <device.h> contains the enumeration IRQn_Type that defines all exceptions and interrupts of the device.
Example:
The following example shows the extension of the interrupt vector table for the LPC1100 device family.
The Device Header File <device.h> configures the Cortex-M or SecurCore processor and the core peripherals with #defines that are set prior to including the file core_<cpu>.h.
The following tables list the #defines along with the possible values for each processor core. If these #defines are missing default values are used.
core_cm0.h
#define | Value Range | Default | Description |
---|---|---|---|
__CM0_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) |
__NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific) |
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
core_cm0plus.h
#define | Value Range | Default | Description |
---|---|---|---|
__CM0PLUS_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) |
__NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific) |
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
core_cm3.h
#define | Value Range | Default | Description |
---|---|---|---|
__CM3_REV | 0x0101 | 0x0200 | 0x0200 | Core revision number ([15:8] revision number, [7:0] patch number) |
__NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific) |
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not |
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
core_cm4.h
#define | Value Range | Default | Description |
---|---|---|---|
__CM4_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) |
__NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific) |
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not |
__FPU_PRESENT | 0 .. 1 | 0 | Defines if a FPU is present or not |
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
core_cm7.h
#define | Value Range | Default | Description | ||||||||||||
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__CM7_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) | ||||||||||||
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not | ||||||||||||
__NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific) | ||||||||||||
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. | ||||||||||||
__FPU_PRESENT | 0 .. 1 | 0 | Defines if a FPU is present or not. See __FPU_DP description below. | ||||||||||||
__FPU_DP | 0 .. 1 | 0 | The combination of the defines __FPU_PRESENT and __FPU_DP determine the whether the FPU is with single or double precision as shown in the table below.
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__ICACHE_PRESENT | 0 .. 1 | 1 | Instruction Chache present or not | ||||||||||||
__DCACHE_PRESENT | 0 .. 1 | 1 | Data Chache present or not | ||||||||||||
__DTCM_PRESENT | 0 .. 1 | 1 | Data Tightly Coupled Memory is present or not |
core_sc000.h
#define | Value Range | Default | Description |
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__SC000_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) |
__NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific) |
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not |
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
core_sc300.h
#define | Value Range | Default | Description |
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__SC300_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) |
__NVIC_PRIO_BITS | 2 .. 8 | 4 | Number of priority bits implemented in the NVIC (device specific) |
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not |
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
core_CM23.h or core_ARMv8MBL.h
#define | Value Range | Default | Description |
---|---|---|---|
__ARMv8MBL_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) |
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not |
__SAUREGION_PRESENT | 0 .. 1 | 0 | Defines if SAU regions are present or not |
__VTOR_PRESENT | 0 .. 1 | 0 | Defines if a VTOR register is present or not |
__NVIC_PRIO_BITS | 2 | 2 | Number of priority bits implemented in the NVIC (device specific) |
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
core_CM33.h or core_ARMv8MML.h
#define | Value Range | Default | Description |
---|---|---|---|
__ARMv8MML_REV | 0x0000 | 0x0000 | Core revision number ([15:8] revision number, [7:0] patch number) |
__MPU_PRESENT | 0 .. 1 | 0 | Defines if a MPU is present or not |
__SAUREGION_PRESENT | 0 .. 1 | 0 | Defines if SAU regions are present or not |
__FPU_PRESENT | 0 .. 1 | 0 | Defines if a FPU is present or not |
__NVIC_PRIO_BITS | 2 .. 8 | 3 | Number of priority bits implemented in the NVIC (device specific) |
__Vendor_SysTickConfig | 0 .. 1 | 0 | If this define is set to 1, then the default SysTick_Config function is excluded. In this case, the file device.h must contain a vendor specific implementation of this function. |
Example
The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.
Defines in the core_cpu.h file identify the version of the CMSIS-Core (Cortex-M) and the processor used. The following shows the defines in the various core_cpu.h files that may be used in the Device Header File <device.h> to verify a minimum version or ensure that the right processor core is used.
core_cm0.h
core_cm0plus.h
core_cm3.h
core_cm4.h
core_cm7.h
core_sc000.h
core_sc300.h
core_ARMv8MBL.h
core_ARMv8MML.h
The Device Header File <device.h> contains for each peripheral:
The section Peripheral Access shows examples for peripheral definitions.
The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the Device Header File <device.h> may contain functions to access device-specific peripherals. The system_Device.h Template File which is provided as part of the CMSIS specification is shown below.
/**************************************************************************//** * @file <Device>.h * @brief CMSIS Cortex-M# Core Peripheral Access Layer Header File for * Device <Device> * @version V5.00 * @date 10. January 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may * not use this file except in compliance with the License. * You may obtain a copy of the License at * * www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an AS IS BASIS, WITHOUT * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef <Device>_H /* ToDo: replace '<Device>' with your device name */ #define <Device>_H #ifdef __cplusplus extern "C" { #endif /* ToDo: replace '<Vendor>' with vendor name; add your doxyGen comment */ /** @addtogroup <Vendor> * @{ */ /* ToDo: replace '<Device>' with device name; add your doxyGen comment */ /** @addtogroup <Device> * @{ */ /** @addtogroup Configuration_of_CMSIS * @{ */ /* =========================================================================================================================== */ /* ================ Interrupt Number Definition ================ */ /* =========================================================================================================================== */ typedef enum IRQn { /* ======================================= ARM Cortex-M# Specific Interrupt Numbers ======================================== */ /* ToDo: use this Cortex interrupt numbers if your device is a Cortex-M0 / Cortex-M0+ device */ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ /* ToDo: use this Cortex interrupt numbers if your device is a Cortex-M3 / Cortex-M4 / Cortex-M7 device */ Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ /* =========================================== <Device> Specific Interrupt Numbers ========================================= */ /* ToDo: add here your device specific external interrupt numbers according the interrupt handlers defined in startup_Device.s eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */ <DeviceInterrupt>_IRQn = 0, /*!< Device Interrupt */ } IRQn_Type; /* =========================================================================================================================== */ /* ================ Processor and Core Peripheral Section ================ */ /* =========================================================================================================================== */ /* =========================== Configuration of the Arm Cortex-M4 Processor and Core Peripherals =========================== */ /* ToDo: set the defines according your Device */ /* ToDo: define the correct core revision __CM0_REV if your device is a Cortex-M0 device __CM3_REV if your device is a Cortex-M3 device __CM4_REV if your device is a Cortex-M4 device __CM7_REV if your device is a Cortex-M7 device */ #define __CM#_REV 0x0201 /*!< Core Revision r2p1 */ /* ToDo: define the correct core features for the <Device> */ #define __MPU_PRESENT 1 /*!< Set to 1 if MPU is present */ #define __VTOR_PRESENT 1 /*!< Set to 1 if VTOR is present */ #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 0 /*!< Set to 1 if FPU is present */ #define __FPU_DP 0 /*!< Set to 1 if FPU is double precision FPU (default is single precision FPU) */ #define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */ #define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */ #define __DTCM_PRESENT 0 /*!< Set to 1 if DTCM is present */ /** @} */ /* End of group Configuration_of_CMSIS */ /* ToDo: include the correct core_cm#.h file core_cm0.h if your device is a CORTEX-M0 device core_cm3.h if your device is a CORTEX-M3 device core_cm4.h if your device is a CORTEX-M4 device core_cm7.h if your device is a CORTEX-M4 device */ #include <core_cm#.h> /*!< Arm Cortex-M# processor and core peripherals */ /* ToDo: include your system_<Device>.h file replace '<Device>' with your device name */ #include "system_<Device>.h" /*!< <Device> System */ /* ======================================== Start of section using anonymous unions ======================================== */ #if defined (__CC_ARM) #pragma push #pragma anon_unions #elif defined (__ICCARM__) #pragma language=extended #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wc11-extensions" #pragma clang diagnostic ignored "-Wreserved-id-macro" #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning 586 #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Section ================ */ /* =========================================================================================================================== */ /** @addtogroup Device_Peripheral_peripherals * @{ */ /* ToDo: add here your device specific peripheral access structure typedefs following is an example for a timer */ /* =========================================================================================================================== */ /* ================ TMR ================ */ /* =========================================================================================================================== */ /** * @brief Timer (TMR) */ typedef struct { /*!< (@ 0x40000000) TIM Structure */ __IOM uint32_t TimerLoad; /*!< (@ 0x00000004) Timer Load */ __IM uint32_t TimerValue; /*!< (@ 0x00000008) Timer Counter Current Value */ __IOM uint32_t TimerControl; /*!< (@ 0x0000000C) Timer Control */ __OM uint32_t TimerIntClr; /*!< (@ 0x00000010) Timer Interrupt Clear */ __IM uint32_t TimerRIS; /*!< (@ 0x00000014) Timer Raw Interrupt Status */ __IM uint32_t TimerMIS; /*!< (@ 0x00000018) Timer Masked Interrupt Status */ __IM uint32_t RESERVED[1]; __IOM uint32_t TimerBGLoad; /*!< (@ 0x00000020) Background Load Register */ } <DeviceAbbreviation>_TMR_TypeDef; /*@}*/ /* end of group <Device>_Peripherals */ /* ========================================= End of section using anonymous unions ========================================= */ #if defined (__CC_ARM) #pragma pop #elif defined (__ICCARM__) /* leave anonymous unions enabled */ #elif (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning restore #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /* =========================================================================================================================== */ /* ================ Device Specific Peripheral Address Map ================ */ /* =========================================================================================================================== */ /* ToDo: add here your device peripherals base addresses following is an example for timer */ /** @addtogroup Device_Peripheral_peripheralAddr * @{ */ /* Peripheral and SRAM base address */ #define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */ #define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ #define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ /* Peripheral memory map */ #define <DeviceAbbreviation>TIM0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /*!< (Timer0 ) Base Address */ #define <DeviceAbbreviation>TIM1_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1 ) Base Address */ #define <DeviceAbbreviation>TIM2_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2 ) Base Address */ /** @} */ /* End of group Device_Peripheral_peripheralAddr */ /* =========================================================================================================================== */ /* ================ Peripheral declaration ================ */ /* =========================================================================================================================== */ /* ToDo: add here your device peripherals pointer definitions following is an example for timer */ /** @addtogroup Device_Peripheral_declaration * @{ */ #define <DeviceAbbreviation>_TIM0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) #define <DeviceAbbreviation>_TIM1 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) #define <DeviceAbbreviation>_TIM2 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) /** @} */ /* End of group <Device> */ /** @} */ /* End of group <Vendor> */ #ifdef __cplusplus } #endif #endif /* <Device>_H */