library IEEE; use IEEE.std_logic_1164.all; -- defines std_logic types use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics -- http://www.mesanet.com -- -- This program is is licensed under a disjunctive dual license giving you -- the choice of one of the two following sets of free software/open source -- licensing terms: -- -- * GNU General Public License (GPL), version 2.0 or later -- * 3-clause BSD License -- -- -- The GNU GPL License: -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -- -- -- The 3-clause BSD License: -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- * Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- * Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- -- * Neither the name of Mesa Electronics nor the names of its -- contributors may be used to endorse or promote products -- derived from this software without specific prior written -- permission. -- -- -- Disclaimer: -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- -- PIN_WWU_2GBP_72.vhd -- modified by Ralph Stirling -- for WWU 2GBP bioprinter -- 2021-01-12 use work.IDROMConst.all; package PIN_WWU_2GBP_72 is constant ModuleID : ModuleIDType :=( -- Module Tag Module Rev. Module CLock Number Base address Regs per module Strides Multi register bit mask (WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask), (IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask), (QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask), (PWMTag, x"00", ClockHighTag, x"02", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask), (PktUARTTTag, x"00", ClockLowTag, x"08", PktUARTTDataAddr&PadT, PktUARTTNumRegs, x"00", PktUARTTMPBitMask), (PktUARTRTag, x"00", ClockLowTag, x"08", PktUARTRDataAddr&PadT, PktUARTRNumRegs, x"00", PktUARTRMPBitMask), (StepGenTag, x"02", ClockLowTag, x"04", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask), (LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask), (SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT,SSerialNumRegs, x"10", SSerialMPBitMask), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"), (NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000") ); -- P01 IO00 STEP1 -- P03 IO01 DIR1 -- P05 IO02 STEP2 -- P07 IO03 DIR2 -- P09 IO04 STEP3 -- P11 IO05 DIR3 -- P13 IO06 STEP4 -- P15 IO07 DIR4 -- P17 IO08 HVPOL -- P19 IO09 HVPWR = 1 for HV on -- P21 IO10 -- P23 IO11 -- P25 IO12 HOME1 -- P27 IO13 HOME2 -- P29 IO14 HOME3 -- P31 IO15 HOME4 -- P33 IO17 -- P35 IO18 -- P37 IO19 HV-PWM -- P39 IO20 -- P41 IO21 V-FCLK -- P43 IO22 HV-VMON -- P45 IO23 HV-CMON -- P47 IO24 ESTOP-OUT = 0 for operation constant PinDesc : PinDescType :=( -- Base func sec unit sec func sec pin IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 + 00 IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01 + 00 IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02 + 00 IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03 + 00 IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04 + 00 IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05 + 00 IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06 + 00 IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 08 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 09 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 10 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 11 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 12 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 13 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 14 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 15 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 16 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 17 + 00 IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 19 + 00 IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 20 + 00 IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 21 + 00 IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 22 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 23 + 00 IOPortTag & x"00" & NullTag & x"00", -- I/O 00 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 01 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 02 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 03 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 04 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 05 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 06 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 07 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 08 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 09 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 10 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 11 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 12 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 13 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 14 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 15 + 24 -- IOPortTag & x"00" & PktUARTTTag & PktUTDataPin, -- I/O 16 + 24 -- IOPortTag & x"00" & PktUARTRTag & PktURDataPin, -- I/O 17 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 16 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 17 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 18 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 19 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 20 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 21 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 22 + 24 IOPortTag & x"00" & NullTag & x"00", -- I/O 23 + 24 IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 1+48 IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 0+48 IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin,-- I/O 2+48 -- IOPortTag & x"00" & NullTag & x"00", -- I/O 00 + 48 -- IOPortTag & x"00" & NullTag & x"00", -- I/O 01 + 48 -- IOPortTag & x"00" & NullTag & x"00", -- I/O 02 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 03 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 04 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 05 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 06 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 07 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 08 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 09 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 10 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 11 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 12 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 13 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 14 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 15 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 16 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 17 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 18 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 19 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 20 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 21 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 22 + 48 IOPortTag & x"00" & NullTag & x"00", -- I/O 23 + 48 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3 emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin); end package PIN_WWU_2GBP_72;