V. Schematic Driven Cell Layout Using Pyxis

• Introduction

• Prepare your Workspace

• Creating a CMOS NOR Gate Schematically

• Transient Response of the CMOS NOR Gate

• Creating a Symbol of Your Schematic

• Creating the layout of the CMOS NOR gate Schematically Driven

In this tutorial we will use Pyxis Schematic and Pyxis Layout to create a two input CMOS NOR gate. In previous tutorials we have drawn transistors directly from Pyxis Layout. Another way of achieving the same result is to create a schematic and then use Pyxis to automatically construct the shapes necessary that make the circuit.

Make a cell named Tutorial_5 in Tutorials and create a schematic named nor.

Use your knowledge of Pyxis Schematic to create a CMOS NOR gate as shown below.

Check your schematic and fix any errors.

Set the transient analysis as before. Add the necessary forces for the inputs and outputs.

Generate a 100 nanosecond square wave for input 'A'.

Generate a 50 nanosecond square wave for input 'B'.

Make the positive supply voltage equal to 2.5 Volts.

We want to probe inputs A and B and the output Y.

You resulting schematic should look like the one below.

Run the simulation. Evaluate the correctness of your gate. Remember that the equation that governs its operation is expressed as .

End the simulation.

There are two reasons we might want to create a symbol for our NOR gate:

1. Establish connectivity by defining input and output pins.

2. Enable us to use our NOR gate in more complex designs.

Navigate to Add > Generate Symbol... and left click on Choose Shape.... Since there is no NOR shape choose the Or gate. Press OK.

The symbol should automatically have opened in Pyxis Schematic. Select the entire output pin assembly–all three components–by holding down the left mouse and enclosing the pin wire, the text, and the diamond shape. Then move the pin assembly as shown below.

Navigate to Add > Circle and draw a circle between the output and the rest of the body.

Deselect everything (F2). Check the symbol (File > Check Symbol), then save (File > Save Symbol) and then check the symbol once again–the function doesn't actually work the first time. Fix any errors and exit Pyxis Schematic.

At this point we have succesfully created a proper schematic and a proper symbol.

********************************************* START WWU modified verssion

In Project Navigator create a new layout named inv by selecting the inv component, right clicking on it, and from the pop-up menu select New Layout. The New Layout window should open. OK. (Note: The name of the inverter component in the following slides is inv3)

Click on options and set Angle Mode to 90 (only 90 degree angles will be used during layout). Click OK. And click OK in the New Layout window also.

From the top tool bar select Setup > SDL. Select Prompt user when name is not found.

It is beneficial to combine series transistors, such as the NMOS devices in a NAND gate.

Click the Setup... button.

Change the MOS Sharing to Share All and press OK. This will make the program automatically diffusion share the PMOS and NMOS transistors correctly. Otherwise you would have to manually merge them (this can be done either by moving and flipping the transistor into the other one or choosing the correct nets on each transistor and navigating to DLA Device > Edit > Join)

One more setup option is useful. On the top tool bar select Setup > Preferences. On the General setup panel under WorkSpace select Left Right Tiling. Leave all other settings as they are. Click OK.

The Pyxis Layout editor should now look something like this. Note that on the right is a window with the schematic and on the left the actual layout window.

If needed or desired you can zoom the schematic. On the right in the Palette area under DLA Logic is an AutoInst button.

Click AutoInst. This will automatically instantiate your transistors. Make sure nothing is selected when you do that action. The resulting schematic should look like the one below:

The yellow lines show where connections need to be made according to the schematic. You likely will need to move the transistors closer together. Click the lower (N-type) transistor shape, press m, and then move the transistor toward the P device. Horizontally align the poly (green) traces. You can turn on a ruler by clicking the ruler icon on the left tool bar.

The ruler can be removed. On the top tool bar: Edit > Delete > Rulers

The next step is to add “ports” to the leaf cell layout. Ports represent the connecting points to your cell (gate) such as inputs, outputs, Vdd, and ground. They are attached to a particular layer of material such as metal 1 (metal 1 is the default but the layer can be changed). The ports on a layout will be the location where wires can be connected as you assemble leaf cell layouts into larger subsystems.

Click on the top border of the schematic window to select it. On the palette to the right DLA Logic should be displayed as shown a couple pictures above. Two buttons down from the Place button is the Port button. Click on the Port button. A square of material will appear in the Layout window with a label identifying the net it represents. Yellow rubber band lines should appear between the port object and related parts of the layout. For starters, place the ports as shown below. After you place the first port the next port will automatically be ready for placement. In this example, Vdd is at the top left, ground at the bottom left, input on the left and output on the right. Note how left edge of the Vdd, Input, and Ground ports are aligned.

If you want to know which port goes with a particular net in the schematic, make the schematic window active and click on the net of interest. The associated port and rubber band lines in the layout will be highlighted.

To determine to location of an object or point in an object, move the cursor to that location and observe the Cursor x,y coordinates displayed on the tool bar.

The next step is to enlarge the Vdd metal 1 area by stretching the Vdd port. 1) zoom in a bit on the Vdd port. 2) Press the s key to enter stretch mode. 3) Place cursor over lower left corner of the Vdd port and click. 4) Press the v key to initiate alignment mode. 5) Note that cursor location is now relative to the starting point of the stretch. Move cursor up to .32 and click once. 6) Move cursor to the right until the right side of the stretch box is aligned with the right edge of the N-Well. Double click. A red bounding box will be displayed. When you unselect it will turn to blue for metal 1.

Repeat for ground making the width (left to right) of the ground line equal to that of Vdd.

********************************** END of WWU modifications

In previous tutorials we have used Metal 1 to represent the inputs of the inverter. However, for most practical purposes where the cells are going to be used in hierarchical design, we would want the inputs to be something else. Hence, this time and any subsequent times you should use Metal 2 to represent the input and output ports. and the reference node should still be Metal 1.

Go back to your schematic and select the input 'A' branch. Then navigate to DLA Logic > Port. Change the input to Metal 2 by going up two levels from POLYG (you can achieve that by pressing 4 twice). Align it as shown below.

Use IRoute to connect input 'A' to the transistors. You will need to create a connection between POLYG and M2. As with before, click on the iRoute button, then click on the net on the transistor, lay the POLYG towards the input. Close to the input, press 4 twice to make the connection between the two. Repeat from the other transistor but without dropping two levels to POLYG.

Add input 'B' to the left of input 'A' and the output 'Y' to the right of input 'A'. Both of those should be Metal 2! Be sure to leave enough space so there isn't any violation of the rules. Then route the connections.

Select the branch in your schematic and navigate once again to DLA Logic > Port. Place (Metal 1) on top of the PMOS transistor. Align it to the corner as shown below.

Resize to the width of the transistor and change the height to 0.8 μm. Then, make sure that you've left enough space for two NOR gates to touch each others without causing a DRC error because the spacing between the two would be too small. Hence, make your wider by the difference between your out most wire plus 0.09 μm –one way is to access the properties of the shape by pressing q and modifying the width–moving (m) the shape and align it to the middle (v). This will allow for two NOR gates to connect without causing a design rule error because of the minimum spacing between M1 (0.18 μm). It is also of importance to take into account the VIA that's going to be added later. Generally the cell has to have equal width so when you add of them next to each other they align perfectly. Therefore, some trivial calculations have to be done in order to figure out the optimal width of and ground–they are going to be relative to your design. The VIA for adds 0.26 μm to the width of the Metal 1. The VIA for ground adds 0.08 μm to the width of the Metal 1. Assuming that the wire doesn't exceeds the length of the bigger transistor and that we are taking into account the biggest transistor for sizing them, the Metal 1 port for the ground node has to be larger by 0.36 μm.

Similarly, connect the ground to the NMOS transistor. Make sure the sizes of VDD and ground are adhering to the specifications above.

Navigate to DLA Layout > Via > Fill Selected fill with m1nwell VIA and ground with m1psub VIA .

Finish by routing the rest of the circuit and add text to ports (Connectivity > Add Text on Ports... > OK).

Run DRC and LVS as in previous tutorials. DRC will yield three normal errors that have to do with how much POLYG, M1, and M2 are on the layout. Simply there isn't enough. However, you can disregard these for now.

Save your layout and exit Pyxis Layout. Finally, extract the SPICE file as per Tutorial 3, make a "do" file, and simulate the NOR gate to verify its correct operation.