I. Transistor-level Design and Functional Simulation with Pyxis

• Introduction

• Useful Shortcuts for Pyxis Schematic

• Opening Pyxis Project Navigator

• Prepare your Workspace

• Creating a Schematic of a CMOS Inverter

• Simulation of the Transient Response of the Inverter

• Simulation of the Switching Characteristics of the Inverter

In this tutorial we will use the Mentor Graphics Pyxis Design Suite to construct an inverter. The transient response and the dc switching characteristics of the resulting schematic will be simulated to verify the correct operation of the inverter.

This tutorial was initially developed by George Bakirtzis collaborating with Dr. R.H. Klenke at Virginia Commonwealth University. Thank you to Dr. Klenke for allowing WWU to use their work. Modifications have been made to fit the WWU computing environment.

• F2: Deselect everything.

• ESC: Terminate the current operation – use to quit adding wires or elements.

• DEL: Delete a selected element.

• u: Undo previous actions.

• q: Accesses the properties of the element hovered over by the cursor.

• Shift+F7: Change text hovered over by the cursor – used to change net names, port names, and widths.

• Shift+F8: Zoom to fit window.

• Numeric Pad +: Zoom in.

• Numeric Pad -: Zoom out.

• Page Up: Move window up (e.g., object down).

• Page Down: Move window down (e.g., object up).

• CTRL+Page Up: Move window left (e.g., object right).

• CTRL+Page down: Move window right (e.g., object left).

Open a terminal window (Applications > System Tools > Terminal). Create a folder for your project using mkdir. The example name used below is vlsiproject, but choose a meaningful name . Make that the current directory using cd and then start Pyxis Project Navigator.

$ cd ~
$ mkdir vlsiproject
$ cd vlsiproject
$ pyxis_ibm

The initial Pyxis project navigator screen should look something like this:

After Pyxis Project Manager starts, and before you create a project, specify the Technology Library to be used (the library comes as part of a process design kit (PDK). From the tool bar select File > Install > Process Design Kit. This window should open:

Click on the navigator button to the right of Design Kit and navigate to /home/classes/ee434. Select the CMRF8SF folder (note upper case CMRF8SF), which is a technology library, and Click OK.

The window below will appear. (the Destination is grayed out, that is ok).

Click OK if the path to the design kit is ok. Then the following window should open:

No changes needed here, default is ok. Click OK

Create a Project

In the Pyxis Project Navigator go to File > New > Project . In the Project Path box navigate to make the project folder the proper path and type in a file name (i.e. the desired name of your project). Click OK.

Under technology, navigate to choose the CMRF8SF library located at /home/classes/ee434. Single click on CMRF8RF to highlight it:

Click OK.

Your new project window should now look something like this:

Click OK.

A manage External/Logic Libraries window will open.

Click Add Standard Libraries and you should see this:

Click OK.

The next step is to create a project library. On the top tool bar, Select File > New > Library. Name the new library projlib and press OK.

If you look at the directory you created before starting Pyxis (vlsiproject in the examples above) you should see a couple directories (folders) and a couple of “attribute” files:

CMRF8SF/ CMRF8SF.mgc_tech_lib.attr myProject/ myProject.mgc_project.attr

Shown above are two directories plus two files with file extension .attr which mean that the file is a Mentor Graphics attribute file associated with a directory (i.e. folder). The attribute file defines the related directory to be a design object and contains information about it.

The navigator window should look something like this:

(Note: the CMRF8SF entry at the same level as the myProject entry may not be present, but CMRF8SF should be a part of the project when you click on myProject. See next illustration).

Clicking on the myProject object should show a hierarchy something like this:

Right click on projlib libary then select New > Cell. Name the new cell per the leaf cell you are creating, such as inv1, and press OK.

Right click on inv1 then select New > Schematic. Name the schematic inverter and press OK. This will open Pyxis Schematic with an empty sheet.

At the left of the schematic drawing area is a vertical tool bar like this:

On the left tool bar Click on the add Instance Icon

In the Object window, expand CMRF8SF > cmrf8sf > nfet and double click the nfet symbol in the right window. Click OK and place symbol on the schematic.

Pressing escape terminates component placement. Note that a newly placed component is white which indicates that it is selected. Shift F7 unselects all components.

Repeat for the pfet.

Again clicking on Instance, select generic_lib (near bottom on the list), find the components for ground, Vdd, portin, and portout, and place them on the schematic. Each component has one or more pins where connections are made. Don’t place a pin of one part right over the pin of another part. There needs to be wire between pins.

Add wires by pressing w and choosing the starting node. Route the wire to the desired ending node clicking at each point a turn is needed. After you choose the ending node you might need to press ESC to stop the Add Wire function. Press F2 to unselect everything.

Hover over the input or output port, press Shift+F7, and change NET to unique names such as IN and OUT accordingly.

The following box should appear at the bottom of the schematic. Don’t change the Property Name but do change Property Value

Original

After Change

For most components, hovering and using Shift+F7 or first selecting the component (by clicking on it) and then clicking on the icon from the left tool bar opens the Edit Object window in which you can change the Net Name, parameters such as transistor size, etc:

Change the width of the transistors to the desired values. For an inverter, typically the P transistor width will be twice that of the N transistor.

The final schematic should look something like the one below.

Click the Check and Save button on the right hand pallet (or use Ctrl+S) to check for errors and save your design. Then proceed to simulation.

On the right hand pallet left click on Simulation. In the window that opens just click on OK. You should now be in simulation mode. The bar at the top of the schematic area should be green.

Before we run the simulation we will need to perform a little setup work for the simulator to operate properly.

First select circuit nets to which an input voltage needs to be applied. For the inverter this is the Vdd net and the in net. Click on the first net, then hold down the shift key and click on other nets to highlight more than one at a time.

Next, on the left tool bar is an icon with abbreviations AC DC TRAN. Click on it to open the Setup Simulation window:

Here is the simulation setup window that opens:

Under Analysis Selector click the TRAN box and the following screen should be visible. Start and Stop times, print interval, and max step time need to be specified. The values shown below are ok for this demo circuit.

The Libraries, Includes, and Options items can be left with default values. Next, click on Forces in the simulation panel. When this window opens the lower pane will be blank rather than showing the two forces seen below. The forces first have to be defined.

To define a force, click on one of the nets in the “Selection from Schematic” list. Then click the Source Type desired. For example, in the figure above the IN net is selected. Clicking on PULSE in the Source Type box will open another dialog as shown below:

Note that the logic low and high voltages must be defined and the various times. You can use the values shown above for now. Then click the Add button and the force should show up in the lower pane. Repeat for Vdd but select DC as the Source Type and enter a voltage such as 2.5 in the Magnitude box. Again click Add.

Go back to the schematic view. Press function key F2 to clear the selected nets. Then click on the output net to select it.

In the Setup Simulation window click on Outputs. Most of the values can be defaulted except for Task. PLOT should be selected for Task. Click Add and then.

BELOW THIS POINT, DOCUMENT NOT UPDATED FOR WWU.

You should now see the forces on your schematic in simulation mode as shown below.

Click on the input branch and navigate to Setup > Probes add the input signal to be plotted in the simulation. Similarly add the output signal. The resulting setup should look like the one below.

Finally run the simulation by clicking Run ELDO under Schematic Sim > Execute (note that ELDO is the name of the simulator). The results of the simulator will open in a separate application EZwave. If EZwave doesn't launch automatically, navigate to Schematic Sim > Results and left click on View Waves.

In the event that the voltages didn't plot correctly close that window inside EZwave and navigate to Tutorial_1_default > DC. Choose both V(IN) and V(OUT), right click and choose Plot (Stacked).

Select File > Print in EZwave to print your simulation results that verify the correct operation of the inverter. Then close EZwave.

Remark: If you do not see the waveforms shown above close EZwave and in Pyxis Schematic navigate to Schematic Sim > Results > ASCII Files then click on View Complete Log. This will open a notepad window containing the log file of the simulation and it's parameters. You can read the log file to locate errors. Correct your errors and run the simulation again.

Now we will simulate the DC switching characteristics of the inverter. You will program the simulator to sweep the input voltage from 0 V to 2.5 V and plot the resulting output voltage. This plot of vs. will show the switching threshold and noise margin of the design.

First you will need to remove the forces and the probes that were created to simulate the transient response of the CMOS inverter.

Delete each force by navigating to Schematic Sim > Forces/ICs > Manager. Select each force and press DEL.

Delete each probe by navigating to Schematic Sim > Setup > Probes. Select each probe and press DEL.

Navigate to Setup > Analyses .... Deselect the Transient and select DC.

Navigate to Parameters - Sweeps. Remove the t_sweep parameter by left clicking and hitting DEL.

Add a dc_sweep parameter that will define the voltage range and the step of the sweep. The values should be from 0 V to 2.5 V with a step of 0.01 V.

Choose the VDD branch and navigate to Schematic Sim > Forces/ICs > Manager and add a DC force of value 2.5 V.

Add a DC force of value {dc_sweep} to the input signal.

The resulting schematic with the added forces should look like the one below.

Navigate to Schematic Sim > Probes... and left click on Probe All Voltages.

Left click on Run Eldo as before. EZwave should open automatically.

As before we want to plot the input and the output of the inverter. In this case it makes more sense to plot both signals on the same plot since it's the convention for viewing transfer characteristics. If the voltages didn't plot correctly close that window inside EZwave and navigate to Tutorial_1_default > DC. Choose both V(IN) and V(OUT), right click and choose Plot (Overlaid).

In the beginning of the tutorial we changed the width of the NMOS transistor. This was done in order to create a balance between the PMOS and NMOS. Henceforth, the above graph has a crossover of and that is, within error, .

It is of importance to realize that if this fundamental change wasn't made initially vs. would look different.

Close EZwave and change the NMOS transistor width back to 2 μm in simulation mode.

Run a DC analysis once again. You should now notice that occurs earlier than before.