I. Transistor-level Design and Functional Simulation with Pyxis

• Introduction

• Useful Shortcuts for Pyxis Schematic

• Opening Pyxis Project Navigator

• Prepare your Workspace

• Creating a Schematic of a CMOS Inverter

• Simulation of the Transient Response of the Inverter

• Simulation of the Switching Characteristics of the Inverter

In this tutorial we will use the Mentor Graphics Pyxis Design Suite to construct an inverter. The transient response and the dc switching characteristics of the resulting schematic will be simulated to verify the correct operation of the inverter.

This tutorial was initially developed by George Bakirtzis collaborating with Dr. R.H. Klenke at Virginia Commonwealth University. Thank you to Dr. Klenke for allowing WWU to use their work. Modifications have been made to fit the WWU computing environment.

• F2: Deselect everything.

• ESC: Terminate the current operation – use to quit adding wires or elements.

• DEL: Delete a selected element.

• u: Undo previous actions.

• q: Accesses the properties of the element hovered over by the cursor.

• Shift+F7: Change text hovered over by the cursor – used to change net names, port names, and widths.

• Shift+F8: Zoom to fit window.

• Numeric Pad +: Zoom in.

• Numeric Pad -: Zoom out.

• Page Up: Move window up (e.g., object down).

• Page Down: Move window down (e.g., object up).

• CTRL+Page Up: Move window left (e.g., object right).

• CTRL+Page down: Move window right (e.g., object left).

Open a terminal window (Applications > System Tools > Terminal). Create a folder for your project using mkdir. Suggested name is vlsiproject. Make that the current directory using cd and then start Pyxis Navigator.

$ cd ~

$ mkdir vlsiproject

$ cd vlsiproject

$ pyxis_ibm

After Pyxis Project Manager starts, install the process design kit (PDK). From the tool bar select File > Install > Process Design Kit

Click on the navigator button to the right of Design Kit

Click OK and then navigate and select the destination which should be the vlsiproject folder

Click OK.

In the Pyxis Project Navigator go to File > New > Project . In the Project Path box navigate to make the vlsiproject folder the proper path and type in a file name (i.e. the desired name of your project). Click OK.

Under technology, navigate to choose the CMRF8SF library located in the vlsiproject folder:

A manage External/Logic Libraries window will open. Click Add Standard Libraries and then OK.

Your new project window should now look something like this:

Click OK.

On the top tool bar, Select File > New > Library. Name the new library projlib and press OK. The navigator window should look something like this:

Clicking on the myProject object should show a hierarchy something like this:

Right click on projlib libary then select New > Cell. Name the new cell per the leaf cell you are creating, such as inv1, and press OK.

Right click on inv1 then select New > Schematic. Name the schematic inverter and press OK. This will open an empty sheet in Pyxis Schematic.

At the left of the schematic drawing area is a vertical tool bar like this:

On the left is a tool bar. Click on I, add Instance. In the Object window, expand CMRF8SF > cmrf8sf > nfet and click the nfet symbol in the right window. Click OK and place symbol on the schematic.

Repeat for the pfet. The schematic now should look something like the one below.

Again clicking on Instance, select generic_lib, find the components for ground, Vdd, portin, and portout, and place them on the schematic like this:

Add wires by pressing w and choosing the starting node. Lay the wire to the desired ending node. After you choose the ending node you might need to press ESC to stop the Add Wire function.

Hover over the input and output ports and press Shift+F7. Change the names to IN and OUT accordingly.

Also change the width of the transistors to the desired values.

The final schematic should look like the one below.

Check and save the sheet (Ctrl+S), fixing any errors, before you proceed to the simulation.

Go back to the IC Library to the right and left click on Simulation. In the next window just click on OK. You should now be in simulation mode.

Before we run the simulation we will need to perform a little setup work for the simulator to operate properly.

Navigate to Setup > Session > Simulator/Viewer.... Make sure that ELDO is the selected simulator. Also, check Start EZwave automatically.

Navigate to Setup > Session > Environment. Make sure "Automatic check design before netlist" is chosen as shown below.

Left click on Analyses and choose Transient then left click Apply.

Navigate to Parameters - Sweeps. Add a parameter t_sweep, as shown below, to set the step and the stopping time of the simulation.

At this point it's necessary to define an input wave. Select IN on the schematic and navigate to Forces > Manager. Add a pulse input waveform with the attributes shown below. The input will be a pulse which starts low (0 V) at time 0 second then pulses high (2.5 V) 25 nanoseconds later and repeats at 50 nanosecond intervals. The rise time and fall time of the pulse will be 1 nanosecond. Since the stop time is set by default at 100 nanoseconds, you should see two pulses.

Similarly, select the VDD branch and navigate to Forces > Manager. Set the magnitude of a DC force to 2.5 Volts.

You should now see the forces on your schematic in simulation mode as shown below.

Click on the input branch and navigate to Setup > Probes add the input signal to be plotted in the simulation. Similarly add the output signal. The resulting setup should look like the one below.

Finally run the simulation by clicking Run ELDO under Schematic Sim > Execute (note that ELDO is the name of the simulator). The results of the simulator will open in a separate application EZwave. If EZwave doesn't launch automatically, navigate to Schematic Sim > Results and left click on View Waves.

In the event that the voltages didn't plot correctly close that window inside EZwave and navigate to Tutorial_1_default > DC. Choose both V(IN) and V(OUT), right click and choose Plot (Stacked).

Select File > Print in EZwave to print your simulation results that verify the correct operation of the inverter. Then close EZwave.

Remark: If you do not see the waveforms shown above close EZwave and in Pyxis Schematic navigate to Schematic Sim > Results > ASCII Files then click on View Complete Log. This will open a notepad window containing the log file of the simulation and it's parameters. You can read the log file to locate errors. Correct your errors and run the simulation again.

Now we will simulate the DC switching characteristics of the inverter. You will program the simulator to sweep the input voltage from 0 V to 2.5 V and plot the resulting output voltage. This plot of vs. will show the switching threshold and noise margin of the design.

First you will need to remove the forces and the probes that were created to simulate the transient response of the CMOS inverter.

Delete each force by navigating to Schematic Sim > Forces/ICs > Manager. Select each force and press DEL.

Delete each probe by navigating to Schematic Sim > Setup > Probes. Select each probe and press DEL.

Navigate to Setup > Analyses .... Deselect the Transient and select DC.

Navigate to Parameters - Sweeps. Remove the t_sweep parameter by left clicking and hitting DEL.

Add a dc_sweep parameter that will define the voltage range and the step of the sweep. The values should be from 0 V to 2.5 V with a step of 0.01 V.

Choose the VDD branch and navigate to Schematic Sim > Forces/ICs > Manager and add a DC force of value 2.5 V.

Add a DC force of value {dc_sweep} to the input signal.

The resulting schematic with the added forces should look like the one below.

Navigate to Schematic Sim > Probes... and left click on Probe All Voltages.

Left click on Run Eldo as before. EZwave should open automatically.

As before we want to plot the input and the output of the inverter. In this case it makes more sense to plot both signals on the same plot since it's the convention for viewing transfer characteristics. If the voltages didn't plot correctly close that window inside EZwave and navigate to Tutorial_1_default > DC. Choose both V(IN) and V(OUT), right click and choose Plot (Overlaid).

In the beginning of the tutorial we changed the width of the NMOS transistor. This was done in order to create a balance between the PMOS and NMOS. Henceforth, the above graph has a crossover of and that is, within error, .

It is of importance to realize that if this fundamental change wasn't made initially vs. would look different.

Close EZwave and change the NMOS transistor width back to 2 μm in simulation mode.

Run a DC analysis once again. You should now notice that occurs earlier than before.