ENGR-434 Homework #6 - For Wednesday 5/01/19
Read sections 10.3.1, 10.3.2, 10.3.3, 10.3.4 and 10.3.5
Here are problems to work on:
1) Draw a transistor level schematic for figure 10.19b which
is a flip-flop. State how many P and N transistors are needed.
2) Figure 10.25 shows a flip-flop equipped with both reset and set
inputs drawn with a NAND gate symbol which has clock and clock_bar inputs.
Draw the schematic for this interesting NAND gate. Include on this
schematic the size of the transistors that will keep the
output drive the same as a "standard" inverter which has a 1-unit wide
N transistor and a 2-unit wide P transistor.
Larry Aamodt PhD, PE
Professor of Engineering and Computer Science
E.F. Cross School of Engineering
Walla Walla University
Contact:
via email: AamoLa (at) wallawalla.edu
via phone: x2058