ENGR-434 Homework #5 - Due Wednesday 4/24/19
Do problems 4.11, 4.18, 4.21, 4.24
Also, recall that in lab last week we were going to
create a NAND gate. So, if you have not already done so,
create a new cell for the NAND gate (it is ok to be in the same
project as used in lab) and create a schematic and symbol
for it. Then create another cell called nand_test or
similar and initiate a schematic for it. When creating
this schematic you will not use transistors but place
two of your inverters in series driving one input of your NAND gate
(which at this point is just a schematic and symbol).
Connect the second NAND gate input to a DC source
when simulating. Simulate with no load to determine
the parasitic time delay. Also determine the contamination
delay. Note: Doing a NAND cell layout is not part of this assignment.
Larry Aamodt PhD, PE
Professor of Engineering and Computer Science
E.F. Cross School of Engineering
Walla Walla University
Contact:
via email: AamoLa (at) wallawalla.edu
via phone: x2058