ENGR-434 Homework #10 - Due Wednesday 5/22/19
In class we noted that the enable signal for a 16 bit register
might present a 32 minimum size inverter load to the circuit
driving it.
************** Individual homework *********************
As described during class, the problem you each are to solve is
designing a 4:16 decoder with enable that has an output drive
capable of driving the estimated 32 minimum size inverter load
of the 16 bit register with minumum delay (note: if you have a
minimum size gate as the decoder output to drive the register's
enable it is not minimum delay). Recall the discussion in
chapter 4 of the text regarding the best number of stages.
When using the logical effort method, delay was in units
of tau and it is expected that in your work above you will
determine the delay in your decoder driving a register in
units of tau. Use the logical effort and parasitic delay values
as we did in chapter 4 (tables 4.2 and 4.3)) for your
design. After determining a circuit topology and the
number of stages using the logical effort method, estimate actual
time (units of seconds) required to decode a new register
address assuming an IBM 130nm process. Use data from table
8.8 in the text.
Again, each person is to develop a solution, this is not a
group problem. Please write legibly
************** And then a group task *******************
Also due on Wednesday is a team member list. For each
team member identify that individuals responsibility, i.e.
the subsystem (circuit) and any particular tasks they are
responsible for.
Larry Aamodt PhD, PE
Professor of Engineering and Computer Science
E.F. Cross School of Engineering
Walla Walla University
Contact:
via email: AamoLa (at) wallawalla.edu
via phone: x2058