----------------------------------------------------------------------------------
-- Company:        Walla Walla University
-- Engineer:       L.Aamodt
-- 
-- Create Date:    22:08:29 10/19/2020 
-- Design Name:    Example state machine
-- Module Name:    fsm_example_top - Behavioral 
-- Project Name: 
-- Target Devices: Spartan6
-- Tool versions:  ISE 14.7
-- Description:    A simple three state FSM for demonstration
--
-- Dependencies:   WWU FPGA3 board
--
-- Revision: 
-- Revision 1.0 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fsm_example_top is
    Port ( btn10 : in  STD_LOGIC;
           btn12 : in  STD_LOGIC;
           stop : out  STD_LOGIC;
           run : out  STD_LOGIC;
           fast : out  STD_LOGIC;
           mclk : in  STD_LOGIC);
end fsm_example_top;

architecture Behavioral of fsm_example_top is
	type state_type is (A, B, C);
	signal state_reg, next_state : state_type;
	signal x,p : std_logic;
begin
	x <= not btn10;
	p <= not btn12;
		----------- State machine memory ------------
	process(mclk) 
	begin
		if (mclk'event and mclk='1') then
			state_reg <= next_state;
		end if;
	end process;
	   ----------- Next state logic ----------------
	process(x,p,state_reg)
	begin
		case state_reg is
			when A =>
				if ((p = '1') and (x = '1')) then
					next_state <= C;
				elsif ((p = '1') and (x = '0')) then
					next_state <= B;
				else
					next_state <= state_reg;
				end if;
			when B =>
				if (x = '0') then
					next_state <= B;
				else
					next_state <= A;
				end if;
			when C =>
				if (x = '1') then
					next_state <= C;
				else
					next_state <= A;
				end if;
		end case;
	end process;
		----------- Output logic --------------------
	process(state_reg)
	begin
		stop <= '0';	-- default value
		run <= '0';		-- default value
		fast <= '0';	-- default value
		case state_reg is
			when A =>
				stop <= '1';
			when B =>
				run <= '1';
			when C =>
				run <= '1';
				fast <= '1';
		end case;
	end process;	
end Behavioral;