----------------------------------------------------------------------------
--
--      Derived Clock generator.  Generates square waves
--         L.Aamodt
--           As shown, if mclk is 50Mhz t_reg and slowclk are 500hz
--
--	-------------- clock generator -------------------------------------------

	signal clk_next, clk_reg : unsigned(16 downto 0);
	signal t_next, t_reg : std_logic;
	process(mclk)
	begin
		if (mclk'event and mclk='1') then
			clk_reg <= clk_next;
			t_reg <= t_next		--  T-f/f register
		end if;
	end process;
	clk_next <= (others=>'0') when clk_reg=49999 else clk_reg+1;
	t_next <= (not t_reg) when clk_reg = 49999 else t_reg;

	Clk_Buffer: BUFG       -- Put t_reg on a buffered clock line
		port map ( I => t_reg, O => slowclk);
	            -- use slowclk to run flip/flops and counters
					-- slowclk is a square wave
					-- with 500 Hz frequency