----------------------------------------------------------------------------
--      Counter - counts 0,1,2,3 and then starts over at 0      L.Aamodt
----------------------------------------------------------------------------

	signal cnt_next, cnt_reg : unsigned(1 downto 0);
	process(slow_clk)
	begin
		if (slow_clk'event and slow_clk='1') then
			cnt_reg <= cnt_next;
		end if;
	end process;
	cnt_next <= cnt_reg+1;
	--  Note: cnt_reg is the output you need to drive the mux and 2:4 decoder
	--  but you may need to type cast it back to std_logic_vector