ENGR-355 homework #7 - For Wednesday 2/16/22
HW#7 includes reading pages 164-171 of the text if you haven't already.
(this is relevant to Lab 7 that we do Wednesday). Also
study the handout given in class Friday.
Do excercises 1, 2, and 3 on page 180 of the textbook. Also answer
the following questions (which refer to the KL25Z MCU):
4- On the FRDM-KL25Z board, what voltage sources do the Vrefh and Vrefl
pins of the MCU connect to? (see the schematic for this board)
5- What is the allowable frequency range of the internal conversion
clock called ADCK in the KL25Z?
6- The ADCK can be created from one of several source clocks.
Name them.
7- Which bits of which register are used to select the ADCK clock source?
8- The chosen clock source can be divided down to create an ADCK will a
particular frequency (i.e. clock rate). What are the possible division
factors?
9- Which register and which bits need to be set to select using a
hardware trigger from the PIT?
Homework is to be turned in at the start of class Wednesday.
Also read over the description of the ADC and associated
registers in pages 457 to 507 of the KL25 Sub-Family Reference
Manual (reference [2]). Some aspects of ADC operation are more
important than others at this point in our learning and in our
use of the ADC. Pay particular attention to selecting clock source
and rate division, reference voltage, hardware trigger selection,
initiating conversion, and completing conversions. Power control,
conversion time selection, the compare functions, calibration,
and low power modes are more advanced topics we will ignore at this
point. Averaging can be useful.
Larry Aamodt PhD, PE
Professor of Engineering and Computer Science
Walla Walla University
Contact:
via email: AamoLa(at)wallawalla.edu
via phone: x2058